A novel low-voltage operational amplifier for low-power pipelined ADCs |
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Authors: | Fan Mingjun Ren Junyan Guo Yao Li Ning Ye Fan Li Lian |
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Affiliation: | 1. State Key Laboratory of ASIC & System, Fudan University, Shanghai 200433, China;Micro-Nanoelectronics Science and Technology Innovation Platform, Fudan University, Shanghai 200433, China 2. State Key Laboratory of ASIC & System, Fudan University, Shanghai 200433, China |
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Abstract: | A novel low-voltage two-stage operational amplifier employing class-AB architecture is presented. The structure utilizes level-shifters and current mirrors to create the class-AB behavior in the first and second stages. With this structure, the transconductances of the two stages are double compared with the normal configuration without class-AB behaviors with the same current consumption. Thus power can be saved and the operation frequency can be increased. The nested cascode miller compensation and symmetric common-mode feedback circuits are used for large unit-gain bandwidth, good phase margin and stability. Simulation results show that the sample-and-hold of the 12-bit 40-Ms/s pipelined ADC using the proposed amplifier consumes only 5.8 mW from 1.2 V power supply with signal-to-noise-and-distortion ratio 89.5 dB, spurious-free dynamic range 95.7 dB and total harmonic distortion -94.3 dB with Nyquist input signal frequency. |
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Keywords: | low-voltage operational amplifier class-AB two-stage amplifier low-power pipelined ADC |
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