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Cell Signal Distribution and Imprint Reliability in FeRAM with Hybrid Bit Line Architecture
Authors:Keum Hwan Noh  Seaung-Suk Lee  Hee-Bok Kang  Hyuk-Je Jeong  Young-Ho Yang  Sang-Hyun Oh
Affiliation:1. Memory R&2. D Div., Hynix Semiconductor Inc., San 136-1, Ami-ri, Bubal-eub, Ichon-si, Kyoungki-do, 467-701 Korea
Abstract:We have investigated the cell signal distributions of ferroelectric random access memories (FeRAMs) using newly developed design scheme, hybrid bit line architecture and their reliability against imprint degradation. Since FeRAMs have relatively large signal distributions due to nonuniform ferroelectric storage capacitors, cell signal interference between neighboring bit lines severely degrades the sensing signal margin. In order to remove the cross-talk noise, hybrid bit line architecture is developed, which is a combination of the conventional folded and open bit line schemes. The lifetime against imprint degradation of FeRAM devices is also increased using hybrid bit line architecture.
Keywords:FeRAM  hybrid bit line  cross-talk noise  sensing margin  imprint
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