100-Gb/s multiplexing and demultiplexing IC operations in InP HEMT technology |
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| Authors: | Murata K. Sano K. Kitabayashi H. Sugitani S. Sugahara H. Enoki T. |
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| Affiliation: | NTT Photonics Labs., NTT Corp., Kanagawa, Japan; |
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| Abstract: | This paper describes the 100-Gb/s multiplexing operation of a selector IC and demultiplexing operation of a D-type flip-flop (D-FF) using production-level 0.1-/spl mu/m-gate-length InP HEMT IC technology. To boost the operating speed of the selector IC, a selector core circuit directly drives an external 50-/spl Omega/ load, and is included in the output stage. In addition, a test chip containing the selector and a D-FF to confirm error-free operation of these circuits was designed. The fabricated selector IC exhibited clear eye openings at 100 Gb/s, and its error-free operation was confirmed by using the test chip. |
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