首页 | 本学科首页   官方微博 | 高级检索  
     

异步串行通信下位机的FPGA设计与实现
引用本文:孟繁智. 异步串行通信下位机的FPGA设计与实现[J]. 微处理机, 2005, 26(5): 94-96
作者姓名:孟繁智
作者单位:国防科技大学电子科学与工程学院卫星导航定位研发中心,长沙,410073
摘    要:本文介绍了如何使用FPGA来设计异步串行通信中的下位机,重点分析了FPGA中接收模块的设计要点,并且给出了仿真的时序图;同时给出了一种帧通信协议,介绍了微控制器软核PicoBlaze进行协议解释的处理流程.本文设计的异步通信模块在实际系统中运行稳定可靠,证明了设计方案的正确性.

关 键 词:异步串行通信 现场可编程门阵列 微控制器
文章编号:1002-2279(2005)05-0094-03
收稿时间:2004-06-01
修稿时间:2004-06-01

The FPGA Design and Development of the Under Levels Computer in Asynchronous Serial Communication
MENG Fan-zhi. The FPGA Design and Development of the Under Levels Computer in Asynchronous Serial Communication[J]. Microprocessors, 2005, 26(5): 94-96
Authors:MENG Fan-zhi
Abstract:This paper presents how to use the FPGA to design the under levels computer in asynchronous serial communication, and focuses on the key design points of the receiving module in FPGA , together with the simulated timing graphs ; This paper also provides a type of frame communication protocol and the processing flow of the soft microcontroller core PicoBlaze to translate the protocol. The asynchronous serial communication module designed in this paper is running stably and reliably in the real system, which proves the correctness of this paper.
Keywords:Asynchronous serial communication    FPGA    Microcontroller
本文献已被 CNKI 维普 万方数据 等数据库收录!
设为首页 | 免责声明 | 关于勤云 | 加入收藏

Copyright©北京勤云科技发展有限公司  京ICP备09084417号