低偏斜、高变化容忍的层次化无缓冲谐振时钟分布网络

无缓冲谐振时钟分布网络能够最小化同步系统的时钟功耗。但由于没有缓冲器，时钟网络的偏斜受到多方面因素的影响，例如时钟互连线寄生参数的差异，非平衡时钟负载以及工艺、电压温度变化。本文提出了一种层次化的两相无缓冲谐振时钟互连网络结构，将网格型和树型结构的各自优点相结合。在TSMC 65nm标准CMOS工艺下，通过一个流水线乘法器电路分析了该结构时钟网络的偏斜及变化容忍特性。版图后仿真结果表明，层次化时钟网络的偏斜分别比纯网格和纯H树结构时钟网络降低超过75%和65%，而且在非平衡时钟负载或工艺、电压温度变化的情况下，时钟网络偏斜最高小于7ps,不超过整个时钟周期（约760ps）的1%。

Hierarchical distribution network for low skew and high variation-tolerant bufferless resonant clocking

Bufferless resonant clock distribution network can minimize clock power consumption in synchronous system. But without buffers, the clock skew is subject to many factors, such as differential parasitic parameters in clock wires, imbalanced clock load and process-voltage-temperature (PVT) variations. In this paper, we propose a hierarchical interconnection network with two-phase bufferless resonant clock distribution, which mixes advantages of the mesh and the tree architectures. The problems of skew reduction and variation-tolerance in the mixed interconnection network are studied through a pipelined multiplier under TSMC 65nm standard CMOS process. Post-simulation results show that, the hierarchical architecture reduces more than 75% and 65% clock skew compared with pure mesh and pure H-tree network respectively. The maximum skew in the proposed clock distribution is less than 7ps under imbalanced loading and PVT variations, which is no more than 1% of the clock cycle of about 760ps.