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| 8ns 4M_bit高可靠性静态随机存储器 | |
| 引用本文： | 王燕,周云波,张国贤,杨晓花.8ns 4M_bit高可靠性静态随机存储器[J].电子与封装,2010,10(10):16-20. |
| 作者姓名： | 王燕 周云波 张国贤 杨晓花 |
| 作者单位： | 1. 苏州大学电子信息学院,江苏,苏州,215006 2. 江南大学物联网工程学院,江苏,无锡,214122 3. 中国电子科技集团公司第58研究所,江苏,无锡,214035 |
| 摘 要： | 为了满足目前对大容量、高速、高可靠性静态随机存储器(SRAM)越来越多的需求和解决高集成度的SRAM成品率深受生产工艺影响的问题,文章提出了一个256k×16bit高性能SRAM的设计。主要针对以下几个方面进行了描述:采用分级字线的方法和字线局部译码电路,提高速度;采用全PMOS管启动电路、与电源无关的偏置和加入补偿电容的稳压电路消除振荡、提高可靠性、降低功耗;冗余修补电路提高产品成品率。该4M_bitSRAM芯片采用SMIC0.18μm标准工艺,地址转换和存取时间仅为8ns,在SS模型125℃加入寄生参数且每个I/OPAD端口挂50pF电容的情况下,仿真结果表明从地址建立到数据读出仅需要7.16ns。 |
| 关 键 词： | 静态存储器 字线局部译码电路 电压降低转换电路 冗余修补电路 |
8ns 4M_bit Reliability of Static Random Access Memory |
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| WANG Yan,ZHOU Yun-bo,ZHANG Guo-xian,YANG Xiao-hua.8ns 4M_bit Reliability of Static Random Access Memory[J].Electronics & Packaging,2010,10(10):16-20. | |
| Authors: | WANG Yan ZHOU Yun-bo ZHANG Guo-xian YANG Xiao-hua |
| Affiliation: | WANG Yan1,ZHOU Yun-bo2,ZHANG Guo-xian3,YANG Xiao-hua3(1.School of Electronics and Information,Suzhou University,Suzhou 215006,China,2.School of Internet of Things Engineering,Jiangnan University,Wuxi 214122,3.China Electronic Technology Group Corporation No.58 Research Institute,Wuxi 214035,China) |
| Abstract: | In order to meet the current high-capacity, high speed, high reliability, static random access memory （SRAM） and address the needs of solving the problem that more and more highly integrated SRAM yield issues deeply affect the production process, this paper proposes optimal design of word line selection circuit, voltage down converter （VDC） and the redundant repair circuits. The 4M_bit SRAM chips using SMIC 0.18 μ m standard process, address translation and access time is only 8ns. In the case of 125 ℃ and SS model of the circuit by adding parasitic and each I / O PAD port hanging 50pF capacitor, the simulation results show that the data from the address set up to read need only 7.16ns. |
| Keywords: | SRAM local word line decoder VDC redundancy repair circuit |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ | |