| 一种应用于高速高精度模数转换器的比较器 |
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| 引用本文： | 潘小敏,范晓婕,陈玉皎.一种应用于高速高精度模数转换器的比较器[J].电子与封装,2010,10(12):20-22,31. |
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| 作者姓名： | 潘小敏 范晓婕 陈玉皎 |
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| 作者单位： | 1. 无锡市商业职业技术学院,江苏,无锡,214153
2. 中国电子科技集团公司第58研究所,江苏,无锡,214035 |
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| 摘 要： | 文中设计了一种基于CMOS工艺的高速高精度时钟控制比较器。该比较器包含一个全差分开关电容采样级、一级预放大器、动态锁存器及时钟控制反相器。预放大器采用正反馈放大技术保证了增益和速度,锁存器采用两个正反馈锁存器和额外的反馈环路提高了锁存的速度。基于0.18μm 1.8V CMOS工艺进行了设计和仿真,结果表明该比较器可以应用于500 MSPS高精度流水线模数转换器。
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| 关 键 词： | 高速高精度模数转换器 比较器 正反馈 锁存器 |
Comparator Applicable for High Speed High Resolution ADC |
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| PAN Xiao-min,FAN Xiao-jie,CHEN Yu-jiao.Comparator Applicable for High Speed High Resolution ADC[J].Electronics & Packaging,2010,10(12):20-22,31. |
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| Authors: | PAN Xiao-min FAN Xiao-jie CHEN Yu-jiao |
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| Affiliation: | PAN Xiao-min~1,FAN Xiao-jie~2,CHEN Yu-jiao~2 (1.Wuxi Institute of Commerce,Wuxi 214153,China,2.China Electronics Technology Group Corporation No.58 Research Institute,Wuxi 214035,China) |
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| Abstract: | A high speed high resolution clocked comparator circuit in CMOS technology is presented.The comparator includes a preamplifier,a dynamic latch and a clocked inverter.By applying the positive feed-back technique,a sufficient gain as well as speed of the preamplifier is achieved.The speed of the dynamic latch is improved by employing two cross-coupled latch and other feedback circuits.The comparator is designed and simulated in a 0.18μm 1.8V CMOS technology and the result shows that it meets the requirement of a 500 MSPS high resolution pipelined ADC. |
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| Keywords: | high speed high resolution ADC comparator positive feedback latch |
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