| H．264中二进制化编码器的FPGA实现 |
| |
| 引用本文： | 王琨,吴宗勇.H．264中二进制化编码器的FPGA实现[J].国外电子元器件,2009(9):9-11. |
| |
| 作者姓名： | 王琨 吴宗勇 |
| |
| 作者单位： | 福州大学阳光学院; |
| |
| 摘 要： | H．264是最有前景的视频压缩标准，熵编码是其中重要的一环，但算法比较复杂，执行速度不高。对熵编码中的二进制化器进行改进，提出一种基于流水线的FPGA结构。对软件流程进行部分改进以提高速度，采用流水线及并行处理技术设计整个电路。在Spartan3FPGA上实现该电路，编码速度达1bit／cycle，最高时钟频率可达100MHz。
|
| 关 键 词： | 二进制化 FPGA 流水线 H.264 |
FPGA implementation of binarization coder in H.264 |
| |
| WANG Kun,WU Zong-yong.FPGA implementation of binarization coder in H.264[J].International Electronic Elements,2009(9):9-11. |
| |
| Authors: | WANG Kun WU Zong-yong |
| |
| Affiliation: | WANG Kun,WU Zong-yong(College of Yang Guang,Fuzhou University,Fuzhou 350015,China) |
| |
| Abstract: | H.264 is the most promising video compressing standard in the world.Entropy code is one of the key techniques in H.264,but it is complicated and low-speed.So the binarization coder in entropy code is improved and a FPGA architecture based on pipe-line is proposed.For high speed,the original software flow is improved to some extent and a pipe-line and parallel technology is applied in the whole circuit.The circuit is implemented in the Spartan3 FPGA,the coding speed can reach 1bits/cycle and the maximal cloc... |
| |
| Keywords: | binarization FPGA pipe-line H 264 |
| 本文献已被 CNKI 维普 等数据库收录！ |
