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Statistical Design of the Four-MOSFET Structure |
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| Authors: | Tuna B Tarim Mohammed Ismail |
| Affiliation: | (1) Texas Instruments, Inc., 12500 TI Boulevard, Dallas, Texas 75243, USA;(2) Analog VLSI Lab, Department of Electrical Engineering, Ohio State University, Columbus, Ohio, USA |
| Abstract: | The statistical design of the four-MOSFET structure is presented in this paper. The quantitative measure of the effect of mismatch between the four transistors on nonlinearity and offset current is provided through contours. Statistical optimization of the transistor
and
values is demonstrated. The four-MOSFET structure was fabricated through the MOSIS 2  m process using MOS transistor Level-3 model parameters. Experimental results are included in the paper. |
| Keywords: | analog MOS ICs yield enhancement statistical design four-MOSFET structure VLSI |
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