Low-Power Application-Specific Processor for FFT Computations |
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Authors: | Teemu Oskari Pitkänen Jarmo Takala |
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Affiliation: | (1) Department of Computer Systems, Tampere University of Technology, P.O. Box 553, 33101 Tampere, Finland |
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Abstract: | In this paper, a processor architecture tailored for radix-4 and mixed-radix FFT computations is described. The processor
has native support for power-of-two transform sizes. Several optimizations have been used to improve the energy-efficiency
of the processor and experiments show that a programmable solution can possess energy-efficiency comparable to fixed-function
ASICs. |
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Keywords: | |
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