一种提高栅氧化物介电常数的方法

从90 nm技术节点开始,等离子氮化SiON栅氧化层被广泛用作先进的CMOS器件制造。作为传统SiO2栅氧化层的替代材料,SiON栅氧化层因其具有较高的介电常数而能有效地抑制硼等栅极掺杂原子在栅氧化层中的扩散。氮化后热退火处理(Post Nitridation Anneal,PNA)是制备等离子氮化SiON栅氧化层的一个重要步骤,主要用于修复晶格损伤并形成稳定Si-N键,同时在氧化氛围下通过界面的二次氧化反应来修复SiO2/Si界面的损伤。本文通过对传统栅氧制备工艺中PNA单一高温退火工艺的温度、气体氛围进行优化,提供了一种通过提高栅氧化物的氮含量来提其高介电常数的方法。实验数据表明,与传统的制备方法相比,采用本方法所制备的SiON栅氧化层中氮含量可以提高30%以上,栅氧界面态总电荷可减少一个数量级,PMOS器件的NBTI寿命t0.1%和t50%可分别提高15.3%和32.4%。

A Method to Improve the Gate Oxide Dielectric Constant

Plasma nitride SiON films have been widely used as gate dielectric in advanced CMOS device fabrication since 90 nm technology node. As a replacement material for conventional silicon dioxide, it can provide increased dielectric constant and serve as an effective boron barrier. PNA （ Post nitridation anneal ）, a critical step for plasma nitride SiON formation, is used to stabilize plasma incorporated nitrogen radicals and ions through form thermal stable Si-N banding. Furthermore, PNA can repair the damaged Si/SiO2 interface by interface substrate re-oxidation under oxygen contained ambient. The article provided a method to improve the gate oxide nitrogen concentration and dielectric constant through optimizing the process temperature and progress gas ambient of the traditional PNA process. The experimental results show that the nitrogen concentration of gate oxide after optimized the PNA process temperature and progress gas ambient can be increased by 30% or so, the total charge of the interface can decrease an order of magnitude, the PMOS NBTI （ Negative Bias Temperature Instability ）lifetime of tO. 1% and t50% can be increased by 15.3% and 32.4% respectively.