| 基于FPGA的自适应均衡器的研究与设计 |
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| 引用本文： | 李路路,静大海. 基于FPGA的自适应均衡器的研究与设计[J]. 电子设计工程, 2014, 0(5): 92-94 |
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| 作者姓名： | 李路路 静大海 |
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| 作者单位： | 河海大学计算机与信息学院,江苏南京210000 |
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| 摘 要： | 近年来,自适应均衡技术在通信系统中的应用日益广泛,利用自适应均衡技术在多径环境中可以有效地提高数字接收机的性能.为了适应宽带数字接收机的高速率特点,本文阐述了自适应均衡器的原理并对其进行改进.最后使用FPGA芯片和Verilog HDL设计实现了自适应均衡器并仿真验证了新方法的有效性.
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| 关 键 词： | 自适应均衡器 宽带数字接收机 FPGA Verilog HDL |
Design and implementation of equalizer based on FPGA |
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| LI Lu-lu,JING Da-hai. Design and implementation of equalizer based on FPGA[J]. Electronic Design Engineering, 2014, 0(5): 92-94 |
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| Authors: | LI Lu-lu JING Da-hai |
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| Affiliation: | (Computer and Information Institution hohai University, Nanjing 211100, China) |
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| Abstract: | In recent years,the technology of adaptive equalizer has been used largely in the communication systems.Using adaptive equalization in muhipath fading situation can effectively improve the receiver performance.This papedescribes the principle of the adaptive equalizer and be Improve it to accommodate the high rate of the wideband digital receiver,Finally design adaptive equalizer and simulation with FPGA and Verilog HDL to verify its validity. |
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| Keywords: | adaptive equalizer wideband digital receiver FPGA Verilog HDL |
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