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Parallelised max-Log-Map model |
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| Authors: | Loo KK Salman K Alukaidey T Jimaa SA |
| Affiliation: | Dept. of ECEE, Hertfordshire Univ., Hatfield; |
| Abstract: | A parallelised max-Log-MAP model (P-max-Log-MAP) that exploits the sub-word parallelism and very long instruction word architecture of a microprocessor or a digital signal processor (DSP) is presented. The proposed model reduces considerably the computational complexity of the max-Log-MAP algorithm; and therefore facilitates easy implementation |
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