| 一种基于SOC应用的Rail-to-Rail运算放大器IP核 |
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| 引用本文： | 翟艳,杨银堂,朱樟明,王帆. 一种基于SOC应用的Rail-to-Rail运算放大器IP核[J]. 西安电子科技大学学报(自然科学版), 2005, 32(1): 112-115 |
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| 作者姓名： | 翟艳 杨银堂 朱樟明 王帆 |
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| 作者单位： | 西安电子科技大学 宽禁带半导体材料与器件教育部重点实验室，陕西 西安 710071 |
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| 基金项目： | 国家部委预研基金资助项目(51408010601DZ01) |
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| 摘 要： | 采用上华0.6μm DPDM CMOS工艺，设计实现了一种基于片上系统应用的低功耗、高增益Rail-to-Rail运算放大器IP核．基于BSIM3V3 Spice模型，采用Hspice对整个电路进行仿真，在5V的单电源电压工作条件下，直流开环增益达到107.8dB，相位裕度为62.4°，单位增益带宽为4.3MHz，功耗只有0.34mW．
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| 关 键 词： | Rail-to-Rail CMOS 运算放大器 IP核 片上系统 |
| 文章编号： | 1001-2400(2005)01-0112-04 |
A rail-to-rail operational amplifier IP core for SOC application |
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| ZHAI Yan,YANG Yin-tang,ZHU Zhang-ming,WANG Fan. A rail-to-rail operational amplifier IP core for SOC application[J]. Journal of Xidian University, 2005, 32(1): 112-115 |
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| Authors: | ZHAI Yan YANG Yin-tang ZHU Zhang-ming WANG Fan |
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| Affiliation: | Ministry of Edu. Key Lab. of Wide Band-Gap Semiconductor Materials and Devices,Xidian Univ., Xi′an710071， China |
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| Abstract: | Based on SOC application, a Rail-to-Rail operational amplifier IP core with a low-power and a high gain is presented. The operational amplifier will be realized in the CSMC 0.6μm DPDM CMOS process. The whole circuit is simulated with the BSIM3V3 Spice model in Hspice. With a single power supply of 5V in simulation, it is shown that the Rail-to-Rail operational amplifier has an open loop gan of 107. 8dB, a phase margin of 62. 4 degrees and a unit gain bandwidth of 4.3MHz, with the static power dissipation being only 0.34mW. |
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| Keywords: | Rail-to-Rail CMOS operational amplifier IP core SOC |
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