基于FPGA的OBS边缘节点总线控制硬件设计

给出了一种OBS边缘节点总线控制的硬件设计方案。该方案采用循环四次握手的方式完成主模块与其它从模块的通信,用轮询的方式把几个可能引起时序上冲突的信号,按顺序分配到不同的时钟周期上。整个方案以FPGA芯片EP2C20F484C8为基础实现,在Quartus Ⅱ软件上编译通过。仿真结果显示:该方案不仅能够解决时序冲突的问题,而且最高工作频率达到340 MHz,在整个控制模块中占用的逻辑单元(LE)数目仅为0.9%。

Hardware Design of Bus Control Module in OBS Edge Node Based on FPGA

A hardware design of bus control module in OBS edge node is reported.A four cycles handshaking method is circularly adopted by both master and slave module to communicate each other.Moreover,by adopting the polling method,several signals that may cause collisions in the same timing sequence are distributed into different clocks.The whole solution is based on the FPGA chip EP2C20F484C8,and are compiled successfully in the Quartus II software.Simulation result shows that this solution can not only solve the collision problem of timing sequence,but also reach the working clock as much as 340 MHz.In addition,the used logical element(LE) numbers in the bus control module is only 0.9% of the whole control module.