| 数字集成电路设计中的硬件加速验证技术 |
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| 引用本文： | 胡力佳,马琪,徐向阳. 数字集成电路设计中的硬件加速验证技术[J]. 现代电子技术, 2007, 30(11): 145-147 |
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| 作者姓名： | 胡力佳 马琪 徐向阳 |
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| 作者单位： | 1. 杭州电子科技大学,微电子CAD研究所,浙江,杭州,310018
2. 杭州士兰微电子股份有限公司设计所,浙江,杭州,310012 |
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| 摘 要： | 在芯片规模指数式上升和要求面市时间快速缩短的双重压力下,验证已成为数字集成电路设计的瓶颈。利用硬件加速验证技术能很好地解决这一问题。该文论述了硬件加速验证系统的工作原理和组成结构,通过与传统HDL仿真器的比较证明了其优势,并以Aldec公司硬件加速验证工具HES为例说明了硬件加速验证的验证流程。
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| 关 键 词： | 验证 硬件加速验证技术 仿真器 数字集成电路设计 |
| 文章编号： | 1004-373X（2007）11-145-03 |
| 收稿时间： | 2006-10-08 |
| 修稿时间： | 2006-10-08 |
Hardware- based HDL Verification in Digital IC Design |
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| HU Lijia,MA Qi,XU Xiangyang. Hardware- based HDL Verification in Digital IC Design[J]. Modern Electronic Technique, 2007, 30(11): 145-147 |
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| Authors: | HU Lijia MA Qi XU Xiangyang |
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| Affiliation: | 1. CAD Research Center, langzhou Dianzi University, Hangzhou,310018 ,China; 2. Design Center, Hangzhou Silan Microelectronics Co. Ltd. , Hangzhou, 310012, China |
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| Abstract: | Under pressure of the increase of chip scale and the decrease of timing to market,verification has become the bottleneck of digital IC design.Hardware-based HDL verification is a good solution to this problem.This paper describes the principle and the structure of hardware-based HDL verification system,demonstrates its advantages through the comparison with traditional HDL simulators,and introduces the verification flow based on HES of Aldec. |
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| Keywords: | verification hardware-based HDL verification simulator digital IC design |
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