基于正交混淆的多硬件IP核安全防护设计

为了解决集成电路设计中多方合作的成员信息泄漏问题，该文提出一种基于正交混淆的多硬件IP核安全防护方案。该方案首先利用正交混淆矩阵产生正交密钥数据，结合硬件特征的物理不可克隆函数(PUF)电路，产生多硬件IP核的混淆密钥；然后，在正交混淆状态机的基础上，实现多硬件IP核的正交混淆安全防护算法；最后，利用ISCAS-85基准电路和密码算法，验证正交混淆方法的有效性。在台湾积体电路制造股份有限公司(TSMC) 65 nm工艺下测试正交混淆的多硬件IP核方案，正确密钥和错误密钥下的Toggle翻转率小于5%，在较大规模的测试电路中面积和功耗开销占比小于2%。实验结果表明，采用正交混淆的方式能够提高多硬件IP核的安全性，可以有效防御成员信息泄漏、状态翻转率分析等攻击。

Hardware Security for Multi IPs Protection Based on Orthogonal Obfuscation

In order to solve the problem of member information leakage in multi-party cooperative design of integrated circuits, a orthogonal obfuscation scheme of multi-hardware IPs core security protection is proposed. Firstly, the orthogonal obfuscation matrix generates orthogonal key data, and the obfuscated key of the hardware IP core is designed with the physical feature of the Physical Unclonable Function (PUF) circuit. Then the security of multiple hardware IP cores is realized by the orthogonal obfuscation state machine. Finally, the validity of orthogonal aliasing is verified using the ISCAS-85 circuit and cryptographic algorithm. The multi-hardware IP core orthogonal obfuscation scheme is tested under Taiwan Semiconductor Manufacturing Company (TSMC) 65 nm process, the difference of Toggle flip rate between the correct key and the wrong key is less than 5%, and the area and power consumption of the larger test circuit are less than 2%. The experimental results show that orthogonal obfuscation can improve the security of multi-hardware IP cores, and can effectively defend against member information leakage and state flip rate analysis attacks.