| 用于14位210 MS/s电荷域ADC的采样保持前端电路 |
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| 引用本文： | 陈珍海, 魏敬和, 钱宏文, 于宗光, 苏小波, 薛颜, 张鸿. 用于14位210 MS/s电荷域ADC的采样保持前端电路[J]. 电子与信息学报, 2019, 41(3): 732-738. doi: 10.11999/JEIT180337 |
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| 作者姓名： | 陈珍海 魏敬和 钱宏文 于宗光 苏小波 薛颜 张鸿 |
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| 作者单位： | 1.黄山学院信息工程学院 黄山 245041;;2.中国电子科技集团第五十八研究所 无锡 214035;;3.西安电子科技大学微电子学院 西安 710071;;4.西安交通大学微电子学院 西安 710049 |
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| 摘 要： | 该文提出一种用于电荷域流水线模数转换器(ADC)的高精度输入共模电平不敏感采样保持前端电路。该采样保持电路可对电荷域流水线ADC中由输入共模电平误差引起的共模电荷误差进行补偿。所提出的高精度输入共模电平不敏感采样保持电路被运用于一款14位210 MS/s电荷域ADC中，并在1P6M 0.18 μm CMOS工艺下实现。测试结果显示，该14位ADC电路在210 MS/s条件下对于30.1 MHz单音正弦输入信号得到的无杂散动态范围为85.4 dBc，信噪比为71.5 dBFS，而ADC内核功耗仅为205 mW，面积为3.2 mm2。
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| 关 键 词： | 流水线模数转换器 电荷域 采样保持 低功耗 共模电荷 |
| 收稿时间： | 2018-04-21 |
| 修稿时间： | 2018-11-22 |
Sample and Hold Front-end Circuit for 14-bit 210 MS/s Charge-domain ADC |
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| Zhenhai CHEN, Jinghe WEI, Hongwen QIAN, Zongguang YU, Xiaobo SU, Yan XUE, Hong ZHANG. Sample and Hold Front-end Circuit for 14-bit 210 MS/s Charge-domain ADC[J]. Journal of Electronics & Information Technology, 2019, 41(3): 732-738. doi: 10.11999/JEIT180337 |
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| Authors: | Zhenhai CHEN Jinghe WEI Hongwen QIAN Zongguang YU Xiaobo SU Yan XUE Hong ZHANG |
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| Affiliation: | 1. School of Information Engineering, Huangshan University, Huangshan 245041, China;;2. No.58 Research Institute, China Electronic Technology Group Corporation, Wuxi 214035, China;;3. Microelectronic Institute, Xidian University, Xi’an 710071, China;;4. School of Microelectronic, Xi’an Jiaotong University, Xi’an 710049, China |
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| Abstract: | A high precision common mode level insensitive sample and hold front-end circuit for charge domain pipelined Analog-to-Digital Converter (ADC) is proposed. The sample and hold circuit can be used to compensate the common mode charge errors caused by the variation of input common mode level in charge domain pipelined ADCs. Based on the proposed sample and hold circuit, a 14-bit 210 MS/s charge domain pipelined ADC is designed and realized in a 1P6M 0.18 μm CMOS process. Test results show the 14-bit 210 MS/s ADC achieves the signal-to-noise ratio of 71.5 dBFS and the spurious free dynamic range of 85.4 dBc, with 30.1 MHz input single tone signal at 210 MS/s, while the ADC core consumes the power consumption of 205 mW and occupies an area of 3.2 mm2. |
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| Keywords: | Pipelined Analog-to-Digital Converter (ADC) Charge-domain Sample and hold Low power Common-mode charge |
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