具有高资源利用率特征的改进型查找表电路结构与优化方法

该文着重研究了FPGA芯片中核心模块基本可编程逻辑单元(BLE)的电路结构与优化设计方法，针对传统4输入查找表(LUT)进行逻辑操作和算术运算时资源利用率低的问题，提出一种融合多路选择器的改进型LUT结构，该结构具有更高面积利用率；同时提出一种对映射后网表进行统计的评估优化方法，可以对综合映射后网表进行重新组合，通过预装箱产生优化后网表；最后，对所提结构进行了实验评估和验证。结果表明：与Intel公司Stratix系列FPGA相比，采用该文所提优化结构，在MCNC电路集和VTR电路集下，资源利用率平均分别提高了10.428% 和 10.433%，有效提升了FPGA的逻辑效能。

A Circuit Optimization Method of Improved Lookup Table for Highly Efficient Resource Utilization

The circuit structure optimization method for Basic programmable Logic Element (BLE) of FPGA is studied. Considering finding the solution to the bottleneck problem of low resource utilization efficiency in logic and arithmetic operations with 4-input Look Up Table (LUT), some efforts to improve BLE design based on 4-input LUT are explored. A high area-efficient LUT structure is proposed, and the possible benefits of such a new structure are analyzed theoretically and simulated. Further, a statistical method for evaluation of the post synthesis and mapping netlist is also proposed. Finally, a number of experiments are carried out to assess the proposed structure based on the MCNC and VTR benchmarks. The results show that, compared with Intel Stratix series FPGAs, the optimized structure proposed in this paper improves respectively the area efficiency of the FPGA by 10.428% and 10.433% in average under the MCNC and VTR benchmark circuits.