Effect of via etching process and postclean treatment on via electrical performance |
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| Authors: | Chiew Nyuk Ho Yeow Kheng Lim Higelin Gerald Wang Ling Goh Man Siu Tse Alex See |
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| Affiliation: | (1) School of Materials Engineering, Nanyang Technological University, Nanyang Avenue, 639798, Singapore;(2) School of Electrical and Electronic, Engineering, Nanyang Technological University, Singapore;(3) Technological Development, Chartered Semiconductor Manufacturing Pvt Ltd., 60, Woodlands Industrial Park D, St. 2, 738406, Singapore |
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| Abstract: | The effects of the via etching process as well as the postclean treatment (PCT) on the electrical performance of vias were studied. Stress-migration (SM) tests were carried out to investigate the effect of temperature. Both the thermal and electrical factors were assessed in the wafer-level conventional electromigration (EM) tests. Our results showed that the removal of the TiN antireflection coating (ARC) layer during via etch results in lower initial via resistance, higher resistance to SM, and longer EM lifetime. On the other hand, with additional PCT, the initial via resistance and SM resistance became worse. The CxFy residues1 induced by the PCT step remain at the bottom of the via and degrade the interface properties. However, the EM lifetime seems to be unaffected by these residues. The better EM performance might be related to the removal of the TiOxNy layer by the PCT step. |
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| Keywords: | Via etching process postclean treatment electrical performance of vias stress-migration tests electromigration |
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