NAND-type DRAM-on-SGT |
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| Authors: | Nakamura H Sakuraba H Masuoka F |
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| Affiliation: | Res. Inst. of Electr. Commun., Tohoku Univ., Sendai, Japan; |
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| Abstract: | In this brief, we propose a novel NAND-type DRAM-on-surrounding-gate transistor (SGT) architecture for high-density and low-voltage memory. The cell structure is composed of NAND-type DRAM vertically stacked on an SGT and an SGT-type capacitor. A cell size of 4F/sup 2/ can be achieved. Since it operates as a gain cell, it is possible to obtain a sufficient amount of signal charge. The device was fabricated with a 0.8-/spl mu/m lithography system. |
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