Design and characterization of analog VLSI neural network modules |
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| Authors: | Gowda S.M. Sheu B.J. Choi J. Hwang C.-G. Cable J.S. |
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| Affiliation: | Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA; |
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| Abstract: | A systematic method for testing large arrays of analog, digital, or mixed-signal circuit components that constitute VLSI neural networks is described. This detailed testing procedure consists of a parametric test and a behavioral test. Characteristics of the input neuron, synapse, and output neuron circuits are used to distinguish between faulty and useful chips. Stochastic analysis of the parametric test results can be used to predict chip yield information. Several measurement results from two analog neural network processor designs that are fabricated in 2 μm double-polysilicon CMOS technologies are presented to demonstrate the testing procedure |
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