基于OVM的网络协议处理芯片验证平台的设计

针对一款网络协议处理芯片,为了保证其设计的正确性,提升验证效率,基于OVM架构,通过SystemVerilog语言搭建了具有受约束的随机激励生成、错误注入、覆盖率收集、正确性自检查等功能的验证平台。通过该验证平台对芯片进行了全方位的高效验证,实现了一次流片成功。基于OVM的验证平台具有良好的可重用性和可扩展性,相对于传统的编写定向测试激励的方法,在验证的高效性、完备性上具有显著的优势。

Design of OVM-based verification platform for network protocol processing chip

In order to ensure the design correctness and enhance the verification efficiency of a network protocol processing chip, a verification platform based on OVM is built through SystemVerilog , which has the functions of constrained random generator, fault injection, coverage rate collection, correctness self-check, and so on. The chip is verified completely and efficiently on the verification platform, and the first silicon success is achieved. The OVM-based verification platform has good reusability and expansibility, and compared to traditional directed testing, it has obvious advantages of efficiency and completeness.