| GPS基带芯片中存储器的可测性设计 |
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| 引用本文： | 王红敏, 高勇, 杨媛.GPS基带芯片中存储器的可测性设计[J].电子器件,2009,32(2). |
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| 作者姓名： | 王红敏 高勇 杨媛 |
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| 作者单位： | 西安理工大学电子工程系,西安,710048;西安理工大学电子工程系,西安,710048;西安理工大学电子工程系,西安,710048 |
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| 摘 要： | GPS基带芯片中嵌入的存储器采用存储器内建自测试(Memory Built-in-Self-Test,MBIST)技术进行可测性设计,并利用一种改进型算法对存储器内建自测试电路的控制逻辑进行设计,结果表明整个芯片的测试覆盖率和测试效率均得到显著提高,电路性能达到用户要求,设计一次成功.
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| 关 键 词： | 基带芯片 可测性设计(DFT) 内建自测试(MBIST) 测试覆盖率 |
Design for Testability of Memory in GPS Baseband Chip |
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| WANG Hong-min,GAO Yong,YANG Yuan.Design for Testability of Memory in GPS Baseband Chip[J].Journal of Electron Devices,2009,32(2). |
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| Authors: | WANG Hong-min GAO Yong YANG Yuan |
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| Affiliation: | Department of Electronic Engineering;Xi'an University of Technology;Xi'an 710048;China |
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| Abstract: | The memory built-in self-test technology is used for the design for testability of the memory embedded in GPS baseband chip.The control logic circuit of the memory built-in self-test circuit is designed by an improved algorithm.The results indicate that the testing coverage and testing efficiency of the whole chip are both increased remarkably.The circuit performance meets the user's requirements and this design is successful for the first test. |
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| Keywords: | baseband chip design for testability built-in self test test coverage |
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