A 550-ps access 900-MHz 1-Mb ECL-CMOS SRAM |
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Authors: | Nambu H. Kanetani K. Yamasaki K. Higeta K. Usami M. Nishiyama M. Ohhata K. Arakawa F. Kusunoki T. Yamaguchi K. Hotta A. Homma N. |
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Affiliation: | Central Res. Lab., Hitachi Ltd., Tokyo; |
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Abstract: | An ultrahigh-speed 1-Mb emitter-coupled logic (ECL)-CMOS SRAM with 550-ps clock-access time, 900-MHz operating frequency, and 12-μm2 memory cells has been developed using 0.2-μm BiCMOS technology. Three key techniques for achieving the ultrahigh speed are a BiCMOS word decoder/driver with an nMOS level-shift circuit, a sense amplifier with a voltage-clamp circuit, and a BiCMOS write circuit with a variable-impedance bitline load. The proposed word decoder/driver and sense amplifier can reduce the delay times of the circuits to 54% and 53% of those of conventional circuits. The BiCMOS write circuit can reduce the power dissipation of the circuit by 74% without sacrificing writing speed. These techniques are especially useful for realizing ultrahigh-spaced high-density SRAMs, which will be used as cache and control memories in mainframe computers |
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