Leakage Minimization Technique for Nanoscale CMOS VLSI |
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Authors: | Kyung Ki Kim Yong-Bin Kim Minsu Choi Park N |
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Affiliation: | Northeastern Univ, Boston; |
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Abstract: | Because of the continued scaling of technology and supply-threshold voltage, leakage power has become more significant in power dissipation of nanoscale CMOS circuits. Therefore, estimating the total leakage power is critical to designing low-power digital circuits. In nanometer CMOS circuits, the main leakage components are the subthreshold, gate-tunneling, and reverse-biased junction band-to-band-tunneling (BTBT) leakage currents. |
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