基于130nm PD-SOI工艺存储单元电路的抗辐射加固设计

基于130 nm部分耗尽绝缘体上硅(SOI) CMOS工艺,设计并开发了一款标准单元库.研究了单粒子效应并对标准单元库中存储单元电路进行了抗单粒子辐射的加固设计.提出了一种基于三模冗余(TMR)的改进的抗辐射加固技术,可以同时验证非加固与加固单元的翻转情况并定位翻转单元位置.对双互锁存储单元(DICE)加固、非加固存储单元电路进行了性能及抗辐射能力的测试对比.测试结果显示,应用DICE加固的存储单元电路在99.8 MeV ·cm2 ·mg_1的线性能量转移(LET)阈值下未发生翻转,非加固存储单元电路在37.6 MeV·cm2·mg_1和99.8 MeV·cm2·mg_1两个LET阈值下测试均发生了翻转,试验中两个版本的基本单元均未发生闩锁.结果证明,基于SOI CMOS工艺的抗辐射加固设计(RHBD)可以显著提升存储单元电路的抗单粒子翻转能力.

Radiation Hardened Design for Storage Cell Circuit Based on 130 nm PD-SOI Process

A standard cell library was designed and developed based on 130 nm partially depleted silicon on insulator (PD-SOI) CMOS process. The single event effects was studied, and the storage cell circuit in the standard cell library was designed for single event radiation hardening. An improved radiation hardened technique based on triple modular redundancy (TMR) was proposed,which can simultaneously verify the upset of hardened and unhardened storage cell circuit and locate the position of the upset unit. The performance and anti-radiation ability of storage cell circuits unhardened and hardened by dual inter-locked storage cell (DICE) were tested and compared. The test results show that the storage cell circuit hardened by DICE does not flip at the linear energy transfer (LET) threshold of 99.8 MeV·cm2·mg-1. On the other hand, the unhardened storage unit flips many times at the LET threshold of 37.6 MeV·cm2·mg-1 and 99.8 MeV·cm2·mg-1. During the test experiment no latches happended in the basic units of both of the DFFs. The results prove that the radiation hardened design based on SOI CMOS process can significantly improve the anti-single event upset ability of the storage unit circuit.