超低功耗Q波段低噪声放大器芯片的设计和实现

采用GaAs赝配HEMT单片微波集成电路(MMIC)工艺和堆栈偏置技术设计实现了一款Q波段低噪声放大器(LNA)芯片.该放大器采用4级级联的堆栈偏置拓扑结构,前两级电路在确保较低输入回波损耗的同时优化了放大器的噪声系数,后两级电路则采用最大增益的匹配方式,确保放大器具有良好的增益平坦度和较小的输出回波损耗.该LNA芯片最终尺寸为3 250 μm×1 500 μm,实测结果表明在40～46 GHz工作频率内放大器工作稳定,小信号增益大于23 dB,噪声系数小于3.0 dB,在4.5V工作电压下消耗电流约6 mA.此外,在片实测结果和设计结果符合良好.

Design and Implementation of a Q-Band Low Noise Amplifier Chip with Ultra-Low Power Consumption

A Q-band low noise amplifier (LNA) chip with stacked bias technology was designed and fabricated by GaAs PHEMT monolithic microwave integrated circuit (MMIC) technology.A four stage cascaded bias stacked topology structure was used in this amplifier.The first two stages circuit were designed to achieve low input return loss and best noise figure,and the last two stages,with the maximum gain matching network,could get good gain flatness and low output return loss.The final LNA chip,with the size of 3 250 μm× 1 500 μm,works well from 40 GHz to 46 GHz,gets small signal gain of more than 23 dB and noise figure of less than 3.0 dB.The current is about 6 mA under 4.5 V supply voltage.moreover,the on wafer test results show good agreement with the design results.