高k HfO2栅介质淀积后退火工艺研究

研究了淀积后退火(PDA)工艺(包括退火环境和退火温度)对高介电常数(k)HfO2栅介质MOS电容(MOSCAP)电学特性的影响.通过对比O2和N2环境中,不同退火温度下的HfO2栅介质MOSCAP的C-V曲线发现,高kHfO2栅介质在N2环境中退火时具有更大的工艺窗口.通过对HfO2栅介质MOSCAP的等效氧化层厚度(dEOT)、平带电压(Vfb)和栅极泄漏电流(Ig)等参数进一步分析发现,与O2环境相比,高kHfO2栅介质在N2环境中PDA处理时dEOT和Ig更小、Vfb相差不大,更适合纳米器件的进一步微缩.HfO2栅介质PDA处理的最佳工艺条件是在N2环境中600℃下进行.该优化条件下高kHfO2栅介质MOSCAP的dEOT=0.75 nm,Vnb=0.37 V,Ig=0.27 A/cm2,满足14或16 nm技术节点对HfO2栅介质的要求.

Study on Post Deposition Annealing Process of the High-k HfO2 Gate Dielectric

The effects of post deposition annealing (PDA) process,including the annealing environment and annealing temperature,on the electrical properties of high-k HfO2 gate dielectric MOS capacitor (MOSCAP) were investigated.It is found that the high-k HfO2 gate dielectric has a larger process window when annealed in N2 environment by comparing the C-V curves of the HfO2 gate dielectric MOSCAP under different annealing temperatures in O2 and N2 environments.Based on the further analysis of parameters of the HfO2 gate dielectric MOSCAP,such as the equivalent oxide thickness (dEOT),flat band voltage (Vfb) and gate leakage current (Is),it is found that the high-k HfO2 gate dielectric during the PDA process in N2 environment has smaller dEOT and Ig,and little difference in Vfb compared with that in O2 environment,which is more suitable for further scaling of nano devices.The optimal PDA condition of the HfO2 gate dielectric is at 600 ℃ in N2 environment.Under this optimized condition,the high-k HfO2 gate dielectric MOSCAP achieves a dEOT of 0.75 nm,a Vfb of 0.37 V and a Ig of 0.27 A/cm2,meeting the requirements of 14 or 16 nm technology nodes for the HfO2 gate dielectric.