| 基于FPGA的高帧频面阵CCD驱动控制设计 |
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| 引用本文： | 孙正磊,王晓东,曲洪丰.基于FPGA的高帧频面阵CCD驱动控制设计[J].电子技术应用,2012(7):65-67,71. |
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| 作者姓名： | 孙正磊 王晓东 曲洪丰 |
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| 作者单位： | 1. 中国科学院长春光学精密机械与物理研究所,吉林长春130033;中国科学院研究生院,北京100039
2. 中国科学院长春光学精密机械与物理研究所,吉林长春,130033 |
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| 摘 要： | 针对面阵CCD KAI-1020在高帧频工作模式下的驱动要求,以FPGA作为控制单元及时序发生器,完成CCD高帧频工作模式下的硬件及软件设计,仿真验证了驱动时序的正确性,完成了硬件电路的调试与试验。成像实验表明,该设计满足了CCD KAI-1020在双端口输出模式下成像的各种驱动控制功能,图像分辨率为1 000×1 000,帧频达到48 f/s。
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| 关 键 词： | CCD 高帧频 FPGA |
Design for driving control of high frame rate area array CCD based on FPGA |
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| Sun Zhenglei
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Wang Xiaodong
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Qu Hongfeng.Design for driving control of high frame rate area array CCD based on FPGA[J].Application of Electronic Technique,2012(7):65-67,71. |
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| Authors: | Sun Zhenglei Wang Xiaodong Qu Hongfeng |
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| Affiliation: | 1(1.Changchun Institute of Optics,Fine Mechanics and Physics,Chinese Academy of Sciences,Changchun 130033,China; 2.Graduate School of the Chinese Academy of Sciences,Beijing 100039,China) |
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| Abstract: | According to the requirement of driving the area array CCD KAI-1020 in high frame rate mode,using FPGA as control unit and timing generator,completed the hardware and software design of CCD worked in high frame rate mode.Simulated and validated the correctness of driving timing,accomplished the debugging and experimentation of hardware.The imaging experiments show the design meets the diversified driving control function of CCD KAI-1020 worked in dual-port output mode,the image resolution is 1 000(H)×1 000(V),frame rate is 48 f/s. |
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| Keywords: | CCD high frame rate FPGA |
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