A 6-bit 2 GS/s ADC in 65 nm CMOS

A 6-bit 2 GS/s ADC was implemented using a 65 nm digital CMOS technology. The design is based on a single-channel flash ADC architecture, and utilizes interpolating and averaging techniques. A two-stage CML-CMOS high-speed hybrid comparator is designed for optimal speed and power performance. The total power consumption of the converter is 52 mW and the area is 0.24 mm². The ADC achieves 42.5 dB SFDR and 5.2 bit ENOB at input frequency of 123 MHz, and at Nyquist frequency 37.67 dB SFDR and 4.9 bit ENOB.