Electrical characterization and analysis techniques for the high-κ era

Various conventional and novel electrical characterization techniques have been combined with careful, robust analysis to properly evaluate high-κ gate dielectric stack structures. These measurement methodologies and analysis techniques have enhanced the ability to separate pre-existing defects that serve as fast transient charging and discharging sites from defects generated with stress. In addition, the differentiation of electrically active bulk high-κ traps, silicon substrate interface traps, and interfacial layer traps has been effectively demonstrated.