A 4-Gb/s/pin low-power memory I/O interface using 4-level simultaneous bi-directional signaling

This paper presents a simultaneous bi-directional (SBD) 4-level I/O interface for high-speed DRAMs. The data rate of 4 Gb/s/pin was demonstrated using a 500-MHz clock generator and a full CMOS rail-to-rail power swing. The power consumed by the I/O circuit was measured to be 28 mW/pin, when connected to a 10-pF load, at a 1.8-V supply voltage. The transmitter uses a 4-level push-pull linear output driver and a 4-level automatic impedance controller, achieving the reduction of driver currents and the voltage margin as large as 200 mV. The receiver employs a hierarchical sampling scheme, wherein a differential amplifier selects three out of six reference voltage levels. This scheme ensures minimized sampling power and a wide common-mode sampling range. The 6-level reference voltage for sampling is generated by the combination of the transmitter replica. The proposed I/O interface circuits are fabricated using a 0.10-/spl mu/m, 2-metal layers DRAM process, and the active area is 330 /spl times/ 66 /spl mu/m/sup 2/. It exhibits 200 mV /spl times/ 690 ps eye windows on the given channel with a 1.8-V supply voltage.