双栅双应变沟道全耗尽SOI CMOS的瞬态特性分析

在提出双栅双应变沟道全耗尽SOl MOSFET新结构的基础上,模拟了沟道长度为25nm时基于新结构的CMOS瞬态特性.结果表明,单栅工作模式下,传统应变SiGe(或应变Si)器件的CMOS电路只能实现上升(或下降)时间的改善,而基于新结构的CMOS电路能同时实现上升和下降时间的缩短;双栅模式下,CMOS电路的上升和下降时间较单栅模式有了更进一步的改善,电路性能得以显著提高.

Transient Characteristic Analysis of a Double-Gate Dual-Strained-Channel SOI CMOS

Transient characteristic analysis of a CMOS circuit based on a double-gate dual-strained channel SOI MOSFET with the effective gate length scaling down to 25nm is presented.As a result of simulations,by the adoption of a single-gate (SG) control mechanism,the conversion time from logic 1 to logic 0 is shorter for conventional strained-Si CMOS than unstrained CMOS.Furthermore,the conversion time from logic 0 to logic 1 can be reduced by the application of a strained-SiGe CMOS circuit.However,the CMOS circuit based on the novel structure can reduce tHL and tLH simultaneously.By the adoption of a double-gate (DG) control mechanism,the conversion time of the CMOS circuit shows a dramatic reduction compared with the SG control mechanism and the performance of the CMOS circuit can be improved significantly.