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基于单片FPGA的可扩展DVI发送器
引用本文:吴晓铁,俞军,程君侠.基于单片FPGA的可扩展DVI发送器[J].半导体技术,2007,32(12):1060-1064.
作者姓名:吴晓铁  俞军  程君侠
作者单位:复旦大学,专用集成电路与系统国家重点实验室,上海,200433;复旦大学,专用集成电路与系统国家重点实验室,上海,200433;复旦大学,专用集成电路与系统国家重点实验室,上海,200433
摘    要:介绍了当前主流的DVI数字视频协议,特别分析了TMDS的链路结构、信号特性和编码算法.针对目前DVI设计中的不足,给出了一个符合DVI1.0规范的基于单片FPGA的可扩展视频发送器的实现方法,具备某些传统方案无法完成的特性.它充分利用FPGA领域的最新技术,给出了一种基于Xilinx SPARTAN-3A DDR I/O的输出并串转换技术实现方法,克服了FPGA的最高时钟频率限制,极大地提高了运算速度和减少了对系统硬件的需求.

关 键 词:数字视频接口  双倍数据速率  最小变换差分信号  高清晰度多媒体接口
文章编号:1003-353X(2007)12-1060-05
收稿时间:2007-09-25
修稿时间:2007年9月25日

Expandable Single-FPGA-Based DVI Transmitter
WU Xiao-tie,YU Jun,CHENG Jun-xia.Expandable Single-FPGA-Based DVI Transmitter[J].Semiconductor Technology,2007,32(12):1060-1064.
Authors:WU Xiao-tie  YU Jun  CHENG Jun-xia
Abstract:The mainstream protocol of digital visual interface(DVI)especially in TMDS link structure,signal character and encoding algorithm were introduced.An expandable FPGA-based DVI transmitter system according to DVI 1.0 specification to overcome the shortcomings of current DVI designs was presented,its features in some respects that traditional scheme can not reach.The state-of-the-art technologies of FPGA field were adopted in the design and the realization method of an optimized serializer derived from Xilinx SPARTAN-3A DDR I/O was presented.It overcomes the maximum clock frequency limitation,greatly improves the computation speed and reduces the system hardware requirements.
Keywords:DVI  double data rate(DDR)  transition minimized differential signaling(TMDS)  high-definition multimedia interface(HDMI)
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