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A 1.6 Gbyte/s data transfer rate 8 Mb embedded DRAM |
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| Authors: | Miyano S. Numata K. Sato K. Yabe T. Wada M. Haga R. Enkaku M. Shiochi M. Kawashima Y. Iwase M. Ohgata M. Kumagai J. Yoshida T. Sakurai M. Kaki S. Yanagiya N. Shinya H. Furuyama T. Hansen P. Hannah M. Nagy M. Nagarajan A. Rungsea M. |
| Affiliation: | Semicond. Device Eng. Lab., Toshiba Corp., Kawasaki; |
| Abstract: | An 8 Mb embedded DRAM has been developed. The salient feature of this embedded DRAM is page fault tolerance. Accessing across different pages can be performed using a minimum column cycle. This feature is achieved by placing a data latch and a transfer gate between the bit line sense amplifier and the column select gate. This DRAM can be reconfigured as separated 2 Mb units when it is embedded as a macro cell of an ASIC library |
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