| Abstract: | Early estimation of the wiring space requirements for logic chips and chip-carrying packages is essential. The authors propose a way to do this by taking into account the average length of wiring connections, the number of logic units to be wired, and the average number of connections per logic unit. They show that the probability of automatic wiring success is a function of the number of wiring tracks per logic unit, and that logic changes during design and the use of multicell macros increase the required track count. Intentional depopulation of the image, on the other hand, and the use of multilevel metal wiring decrease the required track count and chip size, respectively, for fixed maximum circuit cell count and fixed probability of automatic wiring success. |
