An Analog-Digital Merged Neural Circuit Using Pulse Width Modulation Technique |
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Authors: | Takashi Morie Jun Funakoshi Makoto Nagata Atsushi Iwata |
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Affiliation: | (1) Faculty of Engineering, Hiroshima University, Higashi-hiroshima-shi, 739–8527, Japan;(2) Fujitsu Limited, Kawasaki-shi, 211–8588, Japan |
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Abstract: | This paper presents a neural circuit using PWM technique based on an analog-digital merged circuit architecture. Some new PWM circuit techniques are proposed. A bipolar-weighted summation circuit is described which attains 8-bit precision in SPICE simulation at 5 V supply voltage by compensating parasitic capacitance effects. A high performance differential-type latch comparator which can discriminate 1 mV difference at 100 MHz in SPICE simulation is also described. Next, we present a prototype chip fabricated using a 0.6 m CMOS process. The measurement results demonstrate that the overall precision in the weighted summation and the sigmoidal transformation is 5 bits. A neural network has been constructed using the prototype chips, and the experimental results for realizing the XOR function have successfully verified the basic neural operation. |
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Keywords: | LSI implementation neural networks pulse-width modulation PWM |
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