| 开关磁阻电动机测速电路的VHDL数字化设计 |
| |
| 引用本文： | 周百新,王思聪. 开关磁阻电动机测速电路的VHDL数字化设计[J]. 南京师范大学学报, 2003, 3(2): 46-49 |
| |
| 作者姓名： | 周百新 王思聪 |
| |
| 作者单位： | 南京师范大学电气与电子工程学院,210042,南京;南京师范大学电气与电子工程学院,210042,南京 |
| |
| 摘 要： | 利用数字电路完成对SRD测速电路的设计，并用VHDL，语言进行描述，经过功能仿真，下载到一片FPGA上制成单片数字化测速电路，并在全数字化的SRD系统中使用了该专用测速芯片，其测速精度优良，测速速度优于单片机测速方法。
|
| 关 键 词： | SRD 数字化设计 测速 VHDL |
| 文章编号： | 1672-1292-(2003)02-0046-04 |
| 修稿时间： | 2003-03-17 |
VHDL Digital Design of SRD Speed-measuring Circuit |
| |
| Zhou Baixin,Wang Sicong. VHDL Digital Design of SRD Speed-measuring Circuit[J]. Journal of Nanjing Nor Univ: Eng and Technol, 2003, 3(2): 46-49 |
| |
| Authors: | Zhou Baixin Wang Sicong |
| |
| Abstract: | The SRD speed measuring circuit was designed by digital circuit. VHDL was used to design this circuit. It was downloaded to a FPGA chip after function simulation, for building single piece digital speed measuring circuit. The chip was used in a all digitialized small SRD system and it was found that the precision was high and the speed was much faster than those of single chip computer. |
| |
| Keywords: | SRD digital design speed measuring VHDL |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ |
