| 基于FPGA的数字基带传输位同步恢复 |
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| 引用本文： | 梁芳. 基于FPGA的数字基带传输位同步恢复[J]. 无线电工程, 2011, 41(12): 21-22 |
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| 作者姓名： | 梁芳 |
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| 作者单位： | 陕西理工学院,陕西汉中,723003 |
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| 摘 要： | 提出了一种基于全数字锁相环提取数字基带传输位同步时钟的设计方案,该方案采用环路鉴相器产生误差信号控制本地位同步电路的添加/扣除门在时钟输出的脉冲序列中附加或扣除1个或几个脉冲实现同步。给出了该方案的整体电路,并经VHDL程序设计,在MaxplusⅡ环境下做了时序仿真,从仿真结果分析了设计方法可实现数字基带传输位同步时钟的提取。
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| 关 键 词： | FPGA 位同步 全数字锁相环 |
FPGA Implementation of Bit Synchronization Circuits for DigitalBaseband Transmission |
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| LIANG Fang. FPGA Implementation of Bit Synchronization Circuits for DigitalBaseband Transmission[J]. Radio Engineering of China, 2011, 41(12): 21-22 |
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| Authors: | LIANG Fang |
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| Affiliation: | LIANG Fang(Shaanxi University of Technology,Hanzhong Shaanxi 723003,China) |
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| Abstract: | The FPGA Implementation of bit synchronization circuits for digital baseband transmission is proposed.Extracting method for timing pulse by phase detector error to control synchronized clock phase is discussed.A realization scheme based on FPGA is introduced in detail and the simulation waveform is elucidated.This design method is easy to implement and suitable for high speed applications. |
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| Keywords: | FPGA bit synchronization DPLL |
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