一种基于FPGA技术的高速数字化仪的设计

介绍了一种基于FPGA的高速数字化仪的理论设计和实现方法，从硬件角度给出了设计思路和实现方法．整个系统核心器件包括：高速数模转换芯片，拥有14b精度，150MHz转换速率等性能；高性能FPGA；板载4片32bSDRAM，能够增加采样深度，提高存储速率，实现大数据量的实时存储．使用Verilog语言编写底层FPGA程序．测试结果表明：可以实现可控深度的预采样；ADC有效位达14b，输入10MHz的正弦信号时，通道间相干系数能达到0．9983，信号完整，能满足对高速信号的采集要求．

Design and Implementation of a FPGA-Based High-speed Digitizer

The core components of the system include the ADC chip for achieving 14-bits accuracy and 150MHz converting rate, high- performance FPGA, and the onboard 32-bits SDRAM for increasing the sampling depth to achieve a large amount of data storage in real time. We adopt the Verilog to edit FPGA program. The testing results show that, the digitizer can realize the controllable depth pre-sampling, the inter channel coherence coefficient can reach 0. 998 3 for a 10 MHz sinusoidal input, and the good synchronization performance and the signal integrity can meet the requirements of high speed signal acquisition.