H.264/AVC中CAVLC解码器的硬件设计与实现

设计了一种基于H.264标准的CAVLC解码器,码流输入单元采用桶形移位器,以实现单周期解一个句法元素,在各解码模块中采用码表分割、算术逻辑替代查表、零码字跳转等关键技术,在减少路径延迟和提高系统吞吐率的同时,节省了硬件开销。整个设计采用Verilog语言实现,在XILINX的ISE8.2开发环境下通过FPGA验证,使用Design Compiler在SMIC0.18μm CMOS单元库下综合,时钟最高频率可以达到165MHz。本设计可满足实时解码H.264高清视频的要求。

Hardware design and implementation of CAVLD in H264/AVC

This paper proposes an implementation of CAVLC decoding VLSI architecture for H.264. To decode every syntax element per cycle, the decoder used barrel shifter as part of input buffer module. In the proposed design, we exploit several techniques to shorten critical path, increase data throughput rate, as well as reduce the circuit area. They are table dividing, table elimination by arithmetic, and zero-skipping. We use Verilog language to implement the design, which was verified on ISE8.2 development environment. In addition, Design Compiler is presented to optimize and synthesize the design under SMIC 0.18μm CMOS technology, the highest frequency reached 165 MHz. It is sure that the design meets the real-time processing requirement for H.264 high-definition video decoding.