Parasitic transistor effects in CMOS VLSI |
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Authors: | Chen JY Lewis AG |
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Affiliation: | Xerox, Palo Alto, CA; |
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Abstract: | Parasitic field-effect transistor (FETs) and bipolar junction transistors (BJTs) in a CMOS circuit are described, along with their interactions with each other and their effect on circuit performance. The results are considered to be useful for setting up design rules between n-channel and p-channel active transistors in CMOS IC layout. Novel parasitic transistors associated with next-generation VLSI technologies, such as trench isolation and silicon-on-insulator, are discussed briefly |
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