微处理器体系结构级软错误易感性评估

随着集成电路特征尺寸的缩小和集成度的增加,微处理器的软错误问题越来越严重。为了提高微处理器的可靠性,设计者需要在体系结构设计时精确估算各个部件的软错误率,从而对各部件进行相应的容错设计。本文针对微处理器中的软错误问题,研究了体系结构级软错误易感性估算模型,基于该模型对超标量微处理器主要部件的软错误易感性进行定量分析,并讨论了可靠性与性能的折衷设计。实验结果对微处理器软错误的预防和保护具有一定指导意义,也为微处理器主要部件的容错设计提供了参考。

Evaluating the Microprocessor Architectural Vulnerability to Soft Errors

With the reduction in IC feature size and increase in integration, the soft error problem in microprocessors is becoming more and more serious. In order to improve the reliability of microprocessors, designers need to estimate the soft error rate of various components accurately for their fault tolerance design. In this paper, the estimation model for the microprocessor architectural vulnerability to soft errors is studied. Based on the model, major components’ vulnerability to soft errors in superscalar microprocessors is evaluated. The trade off design between reliability and performance is also discussed. The experimental results can guide microprocessors’ soft error prevention and protection, and can also provide references for the fault tolerance design of major components in microprocessors.