The effects of SiO2 barrier between active layer and substrate on the performance and reliability of polycrystalline silicon thin film transistors

We report on the performance and hot carrier stress (HCS) reliability of n-channel and p-channel poly-Si thin film transisters (TFT)s fabricated on SiO₂-coated 1737 glass or bare 1737 glass substrates. Low-pressure chemical vapor deposited (LPCVD) or atmospheric pressure chemical vapor deposited (APCVD) SiO₂ with different thicknesses are used as the impurity diffusion barrier layers. We have found that the performance and HCS reliability of n-TFTs on SiO₂-coated 1737 glass are superior to those of n-TFTs on bare 1737 glass. P-TFTs on SiO₂-coated 1737 glass, on the other hand, are observed to perform better than p-TFTs on bare 1737 glass substrates, however p-TFTs on SiO₂-coated 1737 glass are seen to undergo larger improvements in their OFF current, I_OFF, following the HCS compared to p-TFTs on bare 1737 glass. We also explore the impact of SiO₂ coating thickness on the performance and HCS reliability of the TFTs. The HCS reliability of the TFTs on SiO₂-coated 1737 glass substrates is observed to depend on the SiO₂ coating thickness. This was explained in terms of a phenomenological model which involves impurity and grain boundary traps. The presence of the former type of traps is controlled by the presence or absence of the SiO₂ coating, whereas the grain boundary traps are proposed to be sensitive to compressive and tensile stresses in the SiO₂ coating layer which are, in turn, dependent on the layer's thickness.