| 一种基于CMOS工艺的电平转换芯片 |
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| 引用本文： | 周子昂,吴定允,徐坤,张利红.一种基于CMOS工艺的电平转换芯片[J].电子与封装,2011,11(3):22-24. |
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| 作者姓名： | 周子昂 吴定允 徐坤 张利红 |
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| 作者单位： | 周口师范学院物理与电子工程系,河南,周口,466001 |
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| 基金项目： | 周口师范学院青年科研基金 |
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| 摘 要： | 基于CSMC 2P2M 0.6 μm CMOS工艺设计了一种电平转换芯片.整体电路采用Hspice和CSMC 2P2M的0.6 μm CMOS工艺的工艺库(06mixddct02v24)仿真,基于CSMC 2P2M 0.6 μm CMOS 工艺完成版图设计,并在一款多功能数字芯片上使用,版图面积为1mm×1mm,并参与...
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| 关 键 词： | CMOS工艺 电平转换芯片 版图设计 |
A Level Conversion Chip in CMOS Process |
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| ZHOU Zi-ang,WU Ding-yun,XU Kun,ZHANG Li-hong.A Level Conversion Chip in CMOS Process[J].Electronics & Packaging,2011,11(3):22-24. |
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| Authors: | ZHOU Zi-ang WU Ding-yun XU Kun ZHANG Li-hong |
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| Affiliation: | ZHOU Zi-ang,WU Ding-yun,XU Kun,ZHANG Li-hong(Department of Physics and Electronics Engireering,Zhoukou Normal University,Zhoukou 466001,China) |
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| Abstract: | A level conversion chip is designed based on CSMC 2P2M 0.66μm CMOS process.The circuit is simulated using Hspice and the process of the CSMC 2P2M 0.6μm CMOS（06 mixddct02v24）,the layout is based on CSMC 2P2M 0.6μm CMOS and is used in a Multi-functional Digital Chip,The chip area is 1mm×1mm.The design has been successfully implemented by participating in the plan of the Multi Project Wafer.Measurements indicate that the wafer achieves the expected goals. |
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| Keywords: | CMOS process level conversion chip layout design |
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