High level synthesis for loop-based BIST |
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Authors: | Xiaowei Li Paul Y. S. Cheung |
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Affiliation: | (1) Department of Computer Science, Peking University, 100871 Beijing, P.R. China;(2) Department of Electrical and Electronic Engineering, The University of Hong Kong, Pokfulam Road, Hong Kong, P.R. China |
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Abstract: | Area and test time are two major overheads encountered duringdata path high level synthesis for BIST. This paper presents an approach to behavioral synthesis for loop-based BIST. By taking into account the requirements of theBIST scheme during behavioral synthesis processes, an area optimal BIST solutioncan be obtained. This approach is based on the use of test resources reusabilitythat results in a fewer number of registers being modified to be test registers. Thisis achieved by incorporating self-testability constraints during register assignmentoperations. Experimental results on benchmarks are presented to demonstrate theeffectiveness of the approach. |
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Keywords: | built-in self-test (BIST) at-speed testing high-level synthesis data path |
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