| 基于Altera FPGA的千兆以太网实现方案 |
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| 引用本文： | 詹俊鹏,李鹏.基于Altera FPGA的千兆以太网实现方案[J].国外电子元器件,2009(2):50-52. |
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| 作者姓名： | 詹俊鹏 李鹏 |
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| 作者单位： | 西安电子科技大学204实验室; |
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| 摘 要： | 网络正在成为当今社会通信的骨干力量，现代化的设备迫切需要解决如何简捷高速的接入问题，描述了基于FPGA的嵌入式技术。利用Ahera公司的千兆以太网IP核，简要介绍使用Ahera的QuartusⅡ和niosⅡ IDE工具的设计流程设计千兆以太网控制器的方案。
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| 关 键 词： | 嵌入式 千兆以太网 以太网媒体控制器 物理层 |
Design method of triple speed ethernet based on Altera FPGA |
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| ZHAN Jun-peng,LI Peng.Design method of triple speed ethernet based on Altera FPGA[J].International Electronic Elements,2009(2):50-52. |
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| Authors: | ZHAN Jun-peng LI Peng |
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| Affiliation: | Laboratory of 204;Xi'an Electronics University of Secience and Technology;Xi'an 710071;China |
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| Abstract: | Network becomes the foundation of modern common communications,its urgent to solve the access to the system with the ethernet simply and efficiently.The paper deals with the technology of embedded system based on the FPGA.Using Altera triple speed ethernet megacore,the paper introduces the design flow of the QuartusII and IDE design tools,designes schcme of triple speed ethernet cotroller. |
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| Keywords: | embedded triple speed ethernet MAC PHY |
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