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基于低成本FPGA的AES密码算法设计
引用本文:黄前山,季晓勇.基于低成本FPGA的AES密码算法设计[J].通信技术,2010,43(9):156-158.
作者姓名:黄前山  季晓勇
作者单位:南京大学,电子科学与工程系,江苏,南京,210093
摘    要:主要介绍在逻辑资源少的现场可编程门阵列(FPGA)上实现高级数据加密标准(AES)算法设计。首先描述了AES加密算法,并在FPGA上优化实现AES算法,设计结构采用多轮加密共用一个轮运算的顺序结构,加密和解密模块共用密钥扩展模块,减少资源占用,在低时钟频率下保持较高的性能。采用了16位的并行总线通信接口,利用先进先出缓冲器(FIFO)对输入输出数据进行缓存。最后通过仿真和实测表明,在50MHz时钟下加解密速率可达530Mb/s。

关 键 词:高级加密标准  现场可编程逻辑阵列  低成本  并行总线接口

Design of AES Encryption Algorithm Based on Low-cost FPGA
HUANG Qian-shan,JI Xiao-yong.Design of AES Encryption Algorithm Based on Low-cost FPGA[J].Communications Technology,2010,43(9):156-158.
Authors:HUANG Qian-shan  JI Xiao-yong
Affiliation:(Department of Electronic Science & Engineering,Nanjing University,Nanjing Jiangsu 210093,China)
Abstract:This paper mainly describes a less-area FPGA implementation of AES (advanced encryption standard) Encryption algorithm.It tells of AES Algorithm,and its optimal implementation on FPGA with a 16-bit parallel bus communication interface.The AES Algorithm is designed in sequential architecture,and the encryption module and the decryption module share one key expansion module,thus to reduce logic area.Simulation and test indicate that,the data throughput rate could reach 530 Mb/s with a 50 MHz clock.
Keywords:AES  FPGA  low-cost  parallel bus interface
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