Structure and applications of field programmable logic arrays

The recent surge in design activity involving microprocessors and microprogramming techniques reflects the growing trend to replace hardwired logic with microcode for gaining system flexibility at lower cost. In this respect, designers have come to rely on ever larger and denser PROMs to fit the demands of their applications, and today PROMs as large as 4K-bits, organized as 512X8 or 1KX4 are readily available. However, a PROM solution in general forces the user to allocate storage for all possible logic combinations of the input variables, whether needed or not. As a result, when dealing with the type of problem requiring the manipulation of more than about 10 logic variables (or Addresses), several IC packages are usually necessary. This quickly renders a PROM solution marginal at best in terms of speed, power, and cost, and in most cases impractical.Fortunately, many combinational and sequential logic designs involve logic functions which are True for only a small subset of the total logic states generated by the controlling variables. It is here that we step in the basic domain of Field Programmable Logic Arrays which, when viewed as Associative memories, exhibit Selective, Concurrent and Multiple addressing modes that enable compressing a set of logic functions to the minimum required states, at substantial savings in hardware. Also, since FPLAs can be programmed in the field by the user, they are more economical and easier to use than mask programmable PLAs, and should find their way quickly in a wider variety of design situations